Attention is currently required from: Marc Jones, Furquan Shaikh, Jonathan Zhang, Jay Talbott, Stefan Reinauer, Angel Pons.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35525 )
Change subject: soc/intel/common/smbus: lock TCO base address on PCH finalize
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/smbus/tco.c:
https://review.coreboot.org/c/coreboot/+/35525/comment/dca9d373_b4a655e4
PS3, Line 59: pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK);
glk fsp sets it
apl datasheet also says "reserved" while apl fsp sets the bit
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