[coreboot-gerrit] Patch set updated for coreboot: 96f65e1 baytrail: use MCRX in iosf access functions

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4909

-gerrit

commit 96f65e104e3da74dced8d6fcee50675e4511e6a2
Author: Aaron Durbin 
Date:   Tue Oct 29 10:57:31 2013 -0500

baytrail: use MCRX in iosf access functions

While most registers accesses don't need the use of the MCRX
    register (upper 24 bits of address) the MCRX register should
    be protected. The reference code could be doing accesses to
    registers that initlaized the MCRX register. Thus, any access
    after that should ensure the MCRX register is initialized
    appropriately.

BUG=None
    BRANCH=None
    TEST=Verified assembly output. Also, built and booted through
         depthcharge.

Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://chromium-review.googlesource.com/174643
    Reviewed-by: Shawn Nematbakhsh 
---
 src/soc/intel/baytrail/baytrail/iosf.h | 1 +
 src/soc/intel/baytrail/iosf.c          | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h
index 920061f..7f0c7f5 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/baytrail/iosf.h
@@ -45,6 +45,7 @@
 #define  IOSF_OPCODE(x) ((x) << 24)
 #define  IOSF_PORT(x) ((0xff & (x)) << 16)
 #define  IOSF_REG(x) ((0xff & (x)) << 8)
+#define  IOSF_REG_UPPER(x) (((~0xff) & (x)))
 #define  IOSF_BYTE_EN_0 0x10
 #define  IOSF_BYTE_EN_1 0x20
 #define  IOSF_BYTE_EN_2 0x40
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index b9f1531..b050eba 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -47,6 +47,7 @@ uint32_t iosf_bunit_read(int reg)
    uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) |
                  IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;

+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
    return read_iosf_reg(MDR_REG);
 }
@@ -57,6 +58,7 @@ void iosf_bunit_write(int reg, uint32_t val)
                  IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;

write_iosf_reg(MDR_REG, val);
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
 }

@@ -66,6 +68,7 @@ uint32_t iosf_dunit_read(int reg)
                  IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) |
                  IOSF_BYTE_EN;

+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
    return read_iosf_reg(MDR_REG);
 }
@@ -81,6 +84,7 @@ uint32_t iosf_dunit_ch1_read(int reg)
                  IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) |
                  IOSF_BYTE_EN;

+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
    return read_iosf_reg(MDR_REG);
 }
@@ -92,6 +96,7 @@ void iosf_dunit_write(int reg, uint32_t val)
                  IOSF_BYTE_EN;

write_iosf_reg(MDR_REG, val);
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
 }

@@ -101,6 +106,7 @@ uint32_t iosf_punit_read(int reg)
                  IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) |
                  IOSF_BYTE_EN;

+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
    return read_iosf_reg(MDR_REG);
 }
@@ -112,5 +118,6 @@ void iosf_punit_write(int reg, uint32_t val)
                  IOSF_BYTE_EN;

write_iosf_reg(MDR_REG, val);
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
    write_iosf_reg(MCR_REG, cr);
 }