EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )
Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level ......................................................................
Patch Set 6:
(7 comments)
https://review.coreboot.org/c/coreboot/+/37685/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/37685/5/src/mainboard/google/dralli... PS5, Line 56: MISCCFG_ENABLE_GPIO_PM_CONFIG
my fault this should pass 0 not MISCCFG_ENABLE_GPIO_PM_CONFIG
Done
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 160:
sure.
Done
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 161: LOCL
I just honor Tim's CL. I don't remember either.
Done
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 163: 5
TOTAL_GPIO_COMM
Done
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 165: _SB.PCI0.CGPM
yes :) I just copy paste
Done
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/lpit.asl:
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 79: /* Enable GPIO PM */ : _SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
Duncan suggest move into common code in https://review.coreboot.org/c/coreboot/+/37665. […]
Ack
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 96: /* Disable GPIO PM */ : _SB.PCI0.LOCL (0)
Same comment as above.
Ack