8 Apr
2021
8 Apr
'21
4:58 p.m.
Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52197 )
Change subject: soc/amd/cezanne: add downcore and SMT disable settings to deviectree ......................................................................
Patch Set 1:
(2 comments)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/52197/comment/f02caa5b_d0caa2bb PS1, Line 15: downcore_mode Are there a set of allowed values? If so, can you please use enum?
https://review.coreboot.org/c/coreboot/+/52197/comment/9de5ce8f_4e051ee5 PS1, Line 16: uint8_t bool?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32
Gerrit-Change-Number: 52197
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