Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010),
same here, I think we can skip a0-a7
See commets in CB:40731
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: PAD_CFG_NF_BUF_TRIG
Most of the PAD_CFG_NF_BUF_TRIG can be replaced with PAD_CFG_NF, as long as BUF setting is don't car […]
Unfortunately, we cannot use the PAD_CFG_NF() macro here because it sets the trig parameter to LEVEL (0 << 25):
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...
This is incorrect because the RXEVCFG field in the DW0 register is set to 2h (Drive '0') by default after a reset. The work to fix this error will take a lot of time, since all motherboards use this macro. Moreover, Google guys are very annoyed if someone changes all these macros :) For this reason, I added a new universal macro - PAD_CFG_NF_BUF_TRIG().