Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32282
Change subject: soc/intel/../../cpu: Remove redundent enable/disable functions ......................................................................
soc/intel/../../cpu: Remove redundent enable/disable functions
This patch removes multiple enable/disable function definitions and make use of single function with argument to know feature status (enable/disable).
Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/icelake/cpu.c 6 files changed, 34 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32282/1
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8f1d933..488b02e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -94,10 +94,12 @@ /* Set Max Non-Turbo ratio if RAPL is disabled. */ if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); - cpu_disable_eist(); + /* Disable speed step */ + cpu_set_eist(FALSE); } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); - cpu_disable_eist(); + /* Disable speed step */ + cpu_set_eist(FALSE); } }
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 47fbc0d..e8c27d8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -197,10 +197,10 @@ }
/* Enable burst mode */ - cpu_enable_burst_mode(); + cpu_burst_mode(TRUE);
/* Enable speed step. */ - cpu_enable_eist(); + cpu_set_eist(TRUE);
/* Set P-State ratio */ cpu_set_p_state_to_turbo_ratio(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7c06d25..01386dd 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -269,10 +269,8 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf && conf->eist_enable) - cpu_enable_eist(); - else - cpu_disable_eist(); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9964f2b..b0061cc 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -185,50 +185,36 @@ }
/* - * Enable Burst mode. + * Program CPU Burst mode + * TRUE = Enable Burst mode. + * FALSE = Disable Burst mode. */ -void cpu_enable_burst_mode(void) +void cpu_burst_mode(bool burst_mode_status) { msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.hi &= ~BURST_MODE_DISABLE; + if (burst_mode_status) + msr.hi &= ~BURST_MODE_DISABLE; + else + msr.hi |= BURST_MODE_DISABLE; wrmsr(IA32_MISC_ENABLE, msr); }
/* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * TRUE = Enable EIST. + * FALSE = Disable EIST. */ -void cpu_disable_burst_mode(void) +void cpu_set_eist(bool eist_status) { msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.hi |= BURST_MODE_DISABLE; - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ + if (eist_status) + msr.lo |= (1 << 16); + else + msr.lo &= ~(1 << 16); wrmsr(IA32_MISC_ENABLE, msr); }
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 5cea96e..23d9909 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -97,24 +97,18 @@ int cpu_get_burst_mode_state(void);
/* - * Enable Burst mode. + * Program CPU Burst mode + * TRUE = Enable Burst mode. + * FALSE = Disable Burst mode. */ -void cpu_enable_burst_mode(void); +void cpu_burst_mode(bool burst_mode_status);
/* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * TRUE = Enable EIST. + * FALSE = Disable EIST. */ -void cpu_disable_burst_mode(void); - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void); - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void); +void cpu_set_eist(bool eist_status);
/* * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index f4ebacf..62bcff6 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -73,10 +73,8 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf->eist_enable) - cpu_enable_eist(); - else - cpu_disable_eist(); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */