build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/11/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/11/src/soc/intel/alderlake/ro... PS11, Line 29: continue; trailing whitespace