Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri
Why do these have to be done by FSP? These are documented EDS registers which can be set by coreboot […]
According to FSP code, the UPD is interface for writing value in IOM_TYPEC_SW_CONFIGURATION_3 according to board design. So I added EDS info as reference for value of this UPD. I think we don't have any issue to use the UPD.
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));
Have you tried doing: […]
We already check if it's possible like Image clock or ISH pins but it's not only for pin mux. The UPD is also used for writing IOM register for IOM to controll the GPIO as AUXP_DC and AUXN_DC as there are many GPIOs options which IOM can use. for GPIO options for IOM to use, refer NF6 for each GPIO in pin mux table.