Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48682 )
Change subject: soc/intel/common/block/pcie/rtd3: Make changes to support S3 ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/48682/comment/48470000_c3b5c5e9 PS2, Line 91: /* Ensure check works for both active low and active high GPIOs. */ : acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); : : acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); : acpigen_write_store_int_to_op(0, LOCAL0_OP); : acpigen_pop_len(); /* If */ : acpigen_write_else(); : acpigen_write_store_int_to_op(1, LOCAL0_OP); : acpigen_pop_len(); /* Else */
You are right. It does.
hm I guess this isn't doing what I wanted anyway, I just copied the same code from before but it needs to account for the fact that power and reset behave differently (power asserted means device is on, reset asserted means device is held in reset) and while most device have GPIOs configured the same way (active high power, active low reset) that isn't guaranteed to be true.