Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46261 )
Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox ......................................................................
soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
This SOC overrides the common PMC device and instantiates the PMC device in the SSDT. It needs to call the common PMC function to provide the IPC mailbox method.
The common PCIe RTD3 driver can also be enabled which will allow mainboards to enable Runtime D3 power control for PCIe devices.
BUG=b:160996445 TEST=boot on volteer with this driver enabled for the NVMe device in the devicetree and disassemble the SSDT to ensure that the RTD3 code is present.
Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/pmc.c 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 4df2e85..0be2225 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06..a7705de 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -119,6 +119,9 @@ acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); acpigen_write_resourcetemplate_footer();
+ /* Define IPC Write Method */ + pmc_acpi_fill_ssdt_ipc_write_method(); + acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */