Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48286 )
Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ......................................................................
Patch Set 17:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... PS17, Line 100: IA32_L3_MASK_1
Questions: […]
Yes you are right. CLOS selector definition says, if bits are set to 00b, no mask will be applied for L3 CQOS. That's how eNEM CAR teardown code is working so far. We thought that it would be ideal to program them to reset defaults back as mentioned in document. What do you suggest?
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... PS17, Line 101: CONFIG_IA32_L3_MASK_1_DEFAULT
I think it is generally wrong to include SoC specific config checks in common code. […]
Ok. This current approach will cause maintenance issues right to keep track of reset defaults for each program. Since CLOS is 0, I think we don't need to touch the CAR exit code. What do you both suggest?
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... PS17, Line 255: 0xffff
Have we confirmed that? Both L3_MASK and SF_QOS_MASK are related to capacity bit masks which are dif […]
Hi Furquan, actually I printed values of L3_MASK & SF_QOS_MASK as post codes on EC console before eNEM code starts. I see the values of 0xfff and 0xffff respectively. I had asked about EDS reset default value mismatching with the one read with Eric. He had mentioned that it needs an update in the document.