Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: pin mux for Display ports ......................................................................
mb/intel/tglrvp: pin mux for Display ports
Add addtional pin mux for eDP for DP portA and enable DP port1. These pin mux were done in FSPs, this pin mux is for bypassing pin mux in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 8638b80..05fb9fef 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,7 +54,14 @@
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* ToDo: Fill early gpio configurations for TPM and WWAN */ + /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ };
const struct pad_config *variant_gpio_table(size_t *num)