Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38696 )
Change subject: vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38 ......................................................................
vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38
Include a more recent set of files from a current FSP build. These are automatically generated.
BUG=b:153675909 TEST=Trembyle builds and boots to payload
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: I6428f618afc2a1cf1c35e93e00f905f90b2cd86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38696 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/fsp/picasso/FspmUpd.h M src/vendorcode/amd/fsp/picasso/FspsUpd.h 2 files changed, 73 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index aa85adc..a2da917 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -21,7 +21,47 @@ /** Offset 0x004C**/ uint32_t serial_port_stride; /** Offset 0x0050**/ uint32_t serial_port_baudrate; /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint8_t UnusedUpdSpace0[168]; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5; + /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope; + /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; + /** Offset 0x0078**/ uint8_t aa_mode_en; + /** Offset 0x0079**/ uint8_t unused2; + /** Offset 0x007A**/ uint8_t unused3; + /** Offset 0x007B**/ uint8_t unused4; + /** Offset 0x007C**/ uint32_t fast_ppt_limit; + /** Offset 0x0080**/ uint32_t slow_ppt_limit; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant; + /** Offset 0x0088**/ uint32_t psi0_current_limit; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit; + /** Offset 0x0090**/ uint32_t thermctl_limit; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit; + /** Offset 0x009C**/ uint32_t sustained_power_limit; + /** Offset 0x00A0**/ uint32_t stapm_time_constant; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time; + /** Offset 0x00A8**/ uint32_t vrm_current_limit; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin; + /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; + /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; + /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; + /** Offset 0x00C1**/ uint8_t system_config; + /** Offset 0x00C2**/ uint8_t core_dldo_bypass; + /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; + /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; + /** Offset 0x00C5**/ uint8_t unused5; + /** Offset 0x00C6**/ uint8_t unused6; + /** Offset 0x00C7**/ uint8_t unused7; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t pspp_policy; + /** Offset 0x00CD**/ uint8_t audio_soundwire; + /** Offset 0x00CE**/ uint8_t UnusedUpdSpace0[50]; /** Offset 0x0100**/ uint16_t Reserved100; /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5a15435..66ea60b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -13,22 +13,38 @@
typedef struct { - /** Offset 0x0020**/ uint32_t pcie_port0_topology; - /** Offset 0x0024**/ uint32_t pcie_port1_topology; - /** Offset 0x0028**/ uint32_t pcie_port2_topology; - /** Offset 0x002C**/ uint32_t pcie_port3_topology; - /** Offset 0x0030**/ uint32_t pcie_port4_topology; - /** Offset 0x0034**/ uint32_t pcie_port5_topology; - /** Offset 0x0038**/ uint32_t pcie_port6_topology; - /** Offset 0x003C**/ uint32_t pcie_sata_topology; - /** Offset 0x0040**/ uint32_t pcie_xgbe1_topology; - /** Offset 0x0044**/ uint32_t pcie_xgbe2_topology; - /** Offset 0x0048**/ uint32_t dp0_connector_type; - /** Offset 0x004C**/ uint32_t dp1_connector_type; - /** Offset 0x0050**/ uint32_t dp2_connector_type; - /** Offset 0x0054**/ uint32_t dp3_connector_type; - /** Offset 0x0058**/ uint32_t emmc0_mode; - /** Offset 0x005C**/ uint8_t UnusedUpdSpace0[196]; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint32_t ddi_descriptor0; + /** Offset 0x0094**/ uint32_t ddi_descriptor1; + /** Offset 0x0098**/ uint32_t ddi_descriptor2; + /** Offset 0x009C**/ uint32_t ddi_descriptor3; + /** Offset 0x00A0**/ uint32_t unused1; + /** Offset 0x00A4**/ uint32_t unused2; + /** Offset 0x00A8**/ uint32_t unused3; + /** Offset 0x00AC**/ uint32_t unused4; + /** Offset 0x00B0**/ uint8_t fch_usb_version_major; + /** Offset 0x00B1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00B2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00BB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00C4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00CD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x00D6**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x00DF**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x00E8**/ uint8_t fch_usb_device_removable; + /** Offset 0x00E9**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x00EA**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x00EB**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x00ED**/ uint8_t unused8; + /** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; + /** Offset 0x00F2**/ uint8_t UnusedUpdSpace0[46]; /** Offset 0x0120**/ uint16_t UpdTerminator; } FSP_S_CONFIG;