[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x/sata: Add legacy mode support

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39828 )

Change subject: sb/intel/bd82x6x/sata: Add legacy mode support
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39828/2/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/sata.c:

https://review.coreboot.org/c/coreboot/+/39828/2/src/southbridge/intel/bd82x... 
PS2, Line 143: 			pci_or_config8(dev, 0x09, 0x05);
> I can put names to all the registers in a separate patch. […]

Angel, feel free to, but please coordinate with Felix. PCI registers below 0x40
are standard registers. This one is PCI_CLASS_PROG and already defined.

For the bits I'd suggest
    #define PI_PRIMARY_MODE_NATIVE          (1 << 0)
    #define PI_SECONDARY_MODE_NATIVE        (1 << 2)

But I have to say, 0x05 seems more readable to me, fits a single line and one
has to look it up in the datasheet anyway to be sure.