Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: binaryPI: implement C bootblock ......................................................................
Patch Set 24:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36914/3/src/cpu/amd/agesa/Kconfig File src/cpu/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/36914/3/src/cpu/amd/agesa/Kconfig@5... PS3, Line 56: depends on C_ENVIRONMENT_BOOTBLOCK
Haven't checked. Did it as sanity check.
No occurrences except car.ld
https://review.coreboot.org/c/coreboot/+/36914/3/src/drivers/amd/agesa/exit_... File src/drivers/amd/agesa/exit_car.S:
https://review.coreboot.org/c/coreboot/+/36914/3/src/drivers/amd/agesa/exit_... PS3, Line 15: : #include <gcccar.inc> : #include <cpu/x86/cache.h> : : .code32 : .globl chipset_teardown_car : : chipset_teardown_car: : pop %esp : : /* Disable cache */ : movl %cr0, %eax : orl $CR0_CacheDisable, %eax : movl %eax, %cr0 : : AMD_DISABLE_STACK : : /* enable cache */ : movl %cr0, %eax : andl $(~(CR0_CD | CR0_NW)), %eax : movl %eax, %cr0 : : jmp *%esp
No problem
Done
https://review.coreboot.org/c/coreboot/+/36914/3/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/nb_util.c:
https://review.coreboot.org/c/coreboot/+/36914/3/src/northbridge/amd/agesa/f... PS3, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2018 Advanced Micro Devices : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ : : #include <device/pci_ops.h> : #include <northbridge/amd/agesa/agesa_helper.h> : : #define GNB_SCRATCH_REG 0x78 : : #define GNB_DEV PCI_DEV(0, 0, 0) : : void *get_ap_entry_ptr(void) : { : return (void *)pci_read_config32(GNB_DEV, GNB_SCRATCH_REG); : } : : void set_ap_entry_ptr(void *entry) : { : pci_write_config32(GNB_DEV, GNB_SCRATCH_REG, (uintptr_t)entry); : }
Okay, thank you for the info. Will try this approach. […]
Utilized BIOSRAM space in FCH