Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35521 )
Change subject: [WIP] intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35521/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pci.c:
https://review.coreboot.org/c/coreboot/+/35521/1/src/southbridge/intel/bd82x... PS1, Line 78: dev->command |= PCI_COMMAND_IO;
Hmm.. I think specs says VGA IO decode is enabled regardless of PCI_COMMAND_IO bit.
No, the spec seems clear to me:
"Forwarding of these accesses is qualified by the I/O Enable and Memory Enable bits in the Command register."
But this also means we should enable MEMORY as well so this makes any sense? I don't understand, btw., why we have these custom enable_resources() here (and the copy in bd82x6x). It seems much like the default implementation beside skipping some subsystem id handling?