Attention is currently required from: Raul Rangel, Andrey Pronin, Kangheui Won, Julius Werner, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 )
Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ......................................................................
Patch Set 8:
(6 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/b8886e3b_97943f58 PS5, Line 645: config RESUME_PATH_SAME_AS_BOOT
I'm checking CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME and it depends on RESUME_PATH_SAME_AS_BOO […]
Done
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/5f36d7c0_993f0702 PS5, Line 12: select CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME
Not if HAVE_ACPI_RESUME is false. […]
Done
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/5c430623_00b5610f PS7, Line 381: PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
Good catch. The GPIO for GSC_SOC_INT_L moved from GPIO_3 to GPIO_85 in the latest schematic. […]
Done
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/7d938ba0_d05bdc73 PS5, Line 230: verstage_mainboard_s0i3_init();
Yes it can hurt. […]
Done
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/c1f016e4_d8e78602 PS6, Line 284: unmap_fch_devices();
Nit: Can be moved inside psp_verstage_s0i3_resume().
Done
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/58870/comment/73d97577_97f57572 PS3, Line 47: depends on TPM2 && RESUME_PATH_SAME_AS_BOOT
OK. Let's not depend on RESUME_PATH_SAME_AS_BOOT for this CL.
Done