Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34368 )
Change subject: amd/stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME ......................................................................
Patch Set 1:
Patch Set 1:
looks to me that this amd board is broken too much.. let me explain the problem that i'm seeing,
when i'm building amd/gardenia board, here is my .config
CONFIG_RELOCATABLE_RAMSTAGE=y CONFIG_RELOCATABLE_MODULES=y CONFIG_NO_STAGE_CACHE=y
now src/lib/Makefile.inc +174 will include cbmem_stage_cache.c although NO_STAGE_CACHE=y
else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c endif
hence below stage_cache function call from src/soc/amd/common/block/s3/s3_resume.c +63 is getting resolve from cbmem_stage_cache.c. do you think this is correct ?
stage_cache_get_raw(STAGE_S3_DATA, base, size);
when i have modified src/lib/Makefile.inc +174 as below,then i'm getting compilation error as stage_cache_get_raw() function is undefined :(
else ifeq ($(CONFIG_USE_CBMEM_STAGE_CACHE),y) ramstage-y += cbmem_stage_cache.c romstage-y += cbmem_stage_cache.c postcar-y += cbmem_stage_cache.c endif
Does this help: diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc index 9efc6bc414..7d950b0b3a 100644 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ b/src/soc/amd/common/block/s3/Makefile.inc @@ -1,6 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y)
-romstage-y += s3_resume.c -ramstage-y += s3_resume.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
endif