[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34120 )

Change subject: soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34120/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34120/2//COMMIT_MSG@10 
PS2, Line 10: This device gets hidden from PCI bus
            : in FSP-S
> "its been recommended" -- by whom?
>
> From coreboot perspective it would have been much cleaner to flag those BARs with ASSIGNED | FIXED in the respective .read_resources. That would have kept them in their pre-programmed values. But.. sounds like the blob takes this "offensive" option.
>
> Is this hiding of PMC forced by FSP (and can you affect future builds to no do that!) ?
>
> PCH_PWRM_BASE_ADDRESS 0xfe000000
>
> I believe that thi is´ below IOAPICs. There is nothing preventing resource allocator from assigning other resources over this, is there?

It gets marked as reserved here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/cannonlake/... to ensure coreboot resource allocator does not assign it to a different device.