Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
Doesn't answer the question :P > are they in use at all? connected to anything?
Answer: yes, they are.
Right settings should be:
# All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3"
# Set all SRCCLKREQ pins as free-use register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "12" # NVME register "PcieClkSrcUsage[2]" = "7" # WIFI register "PcieClkSrcUsage[3]" = "9" # LAN register "PcieClkSrcUsage[4]" = "0xff" register "PcieClkSrcUsage[5]" = "0xff"