[coreboot-gerrit] [M] Change in coreboot[main]: mb/amd/crater: Add missing dxio descriptors

[Ana Carolina Cabral (Code Review)]

Attention is currently required from: Maximilian Brune.

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/87319?usp=email )

Change subject: mb/amd/crater: Add missing dxio descriptors
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Patch Set 4:

(5 comments)

File src/mainboard/amd/crater/Kconfig:

https://review.coreboot.org/c/coreboot/+/87319/comment/3df5e5eb_ccc58a3c?usp... :
PS3, Line 104:
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Fix applied.

https://review.coreboot.org/c/coreboot/+/87319/comment/ccd0111d_56527857?usp... :
PS3, Line 105:
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Done

https://review.coreboot.org/c/coreboot/+/87319/comment/a4cbbe6d_9b1b0e2f?usp... :
PS3, Line 110:
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Fix applied.

https://review.coreboot.org/c/coreboot/+/87319/comment/06282e30_0ad7421c?usp... :
PS3, Line 115:
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Fix applied.

File src/mainboard/amd/crater/port_descriptors_renoir.c:

https://review.coreboot.org/c/coreboot/+/87319/comment/41a39346_b6007672?usp... :
PS3, Line 55: #define dt_dxio_descriptor { \
            : 	.engine_type = PCIE_ENGINE,	\
            : 	.port_present = true,	\
            : 	.start_logical_lane = 0,	\
            : 	.end_logical_lane = 3,	\
            : 	.device_number = 1,	\
            : 	.function_number = 2,	\
            : 	.link_aspm = ASPM_L1,	\
            : 	.link_aspm_L1_1 = true,	\
            : 	.link_aspm_L1_2 = true,	\
            : 	.turn_off_unused_lanes = false,	\
            : 	.clk_req = CLK_REQ5,	\
            : 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},	\
            : }
            : 
            : #define wwan_dxio_descriptor {	\
            : 	.engine_type = PCIE_ENGINE,	\
            : 	.port_present = true,	\
            : 	.start_logical_lane = 2,	\
            : 	.end_logical_lane = 2,	\
            : 	.device_number = 1,	\
            : 	.function_number = 3,	\
            : 	.link_aspm = ASPM_L1,	\
            : 	.link_aspm_L1_1 = true,	\
            : 	.link_aspm_L1_2 = true,	\
            : 	.turn_off_unused_lanes = false,	\
            : 	.clk_req = CLK_REQ2,	\
            : 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},	\
            : }
            : 
            : #define wlan_dxio_descriptor { \
            : 	.engine_type = PCIE_ENGINE,	\
            : 	.port_present = true,	\
            : 	.start_logical_lane = 3,	\
            : 	.end_logical_lane = 3,	\
            : 	.device_number = 2,	\
            : 	.function_number = 2,	\
            : 	.link_aspm = ASPM_L1,	\
            : 	.link_aspm_L1_1 = true,	\
            : 	.link_aspm_L1_2 = true,	\
            : 	.turn_off_unused_lanes = false,	\
            : 	.clk_req = CLK_REQ6,	\
            : 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},	\
            : }
            : 
            : #define tb_dxio_descriptor { \
            : 	.engine_type = PCIE_ENGINE,	\
            : 	.port_present = true,	\
            : 	.start_logical_lane = 4,	\
            : 	.end_logical_lane = 7,	\
            : 	.device_number = 2,	\
            : 	.function_number = 3,	\
            : 	.link_aspm = ASPM_L1,	\
            : 	.link_aspm_L1_1 = true,	\
            : 	.link_aspm_L1_2 = true,	\
            : 	.turn_off_unused_lanes = false,	\
            : 	.clk_req = CLK_REQ4_GFX,	\
            : 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122},	\
            : }
            : 
            : /* XGBE ETHERNET PORTS Entry Port 0*/
            : // XGBE SGMII interface: Physical lane 4, Logical lane 0
            : // NOTE: Ancillary data not yet captured here due to FSP limitations
            : #define xgbe_port0_dxio_descriptor { \
            : 	.port_present = true,	\
            : 	.engine_type = ETHERNET_ENGINE,	\
            : 	.start_logical_lane = 0,	\
            : 	.end_logical_lane = 0,	\
            : }
            : 
            : /* XGBE ETHERNET PORTS Entry Port 1*/
            : // XGBE SGMII interface: Physical lane 5, Logical lane 1
            : // NOTE: Ancillary data not yet captured here due to FSP limitations
            : #define xgbe_port1_dxio_descriptor {	\
            : 	.port_present = true,	\
            : 	.engine_type = ETHERNET_ENGINE,	\
            : 	.start_logical_lane = 1,	\
            : 	.end_logical_lane = 1,	\
            : }
>

Fix applied.