[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Add ASYNC_FILE_LOADING

[Paul Fagerburg (Code Review)]

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58861 )

Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING
......................................................................

soc/amd/cezanne: Add ASYNC_FILE_LOADING

This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.

BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.

Signed-off-by: Raul E Rangel 
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 11 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index f36f912..a09e9f9 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -19,7 +19,6 @@
    select CPU_INFO_V2
    select DRIVERS_USB_ACPI
    select DRIVERS_I2C_DESIGNWARE
-	select COOP_MULTITASKING
    select DRIVERS_USB_PCI_XHCI
    select FSP_COMPRESS_FSP_M_LZMA
    select FSP_COMPRESS_FSP_S_LZMA
@@ -31,7 +30,6 @@
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
    select PARALLEL_MP_AP_WORK
-	select PAYLOAD_PRELOAD
    select PLATFORM_USES_FSP2_0
    select PROVIDES_ROM_SHARING
    select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
@@ -53,7 +51,6 @@
    select SOC_AMD_COMMON_BLOCK_I2C
    select SOC_AMD_COMMON_BLOCK_IOMMU
    select SOC_AMD_COMMON_BLOCK_LPC
-	select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
    select SOC_AMD_COMMON_BLOCK_MCAX
    select SOC_AMD_COMMON_BLOCK_NONCAR
    select SOC_AMD_COMMON_BLOCK_PCI
@@ -194,6 +191,17 @@
      Sets the size of DRAM allocation for verstage in linker script if
      running as a separate stage on x86.

+config ASYNC_FILE_LOADING
+	bool "Loads files from SPI asynchronously"
+	select COOP_MULTITASKING
+	select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+	select PAYLOAD_PRELOAD
+	help
+	  When enabled, the platform will use the LPC SPI DMA controller to
+	  asynchronously load contents from the SPI ROM. This will improve
+	  boot time because the CPUs can be performing useful work while the
+	  SPI contents are being preloaded.
+
 config RAMBASE
    hex
    default 0x10000000