Attention is currently required from: Bora Guvendik, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 )
Change subject: soc/intel/alderlake: Inject Pre-CPU reset TS into timestamp_table ......................................................................
Patch Set 7:
(2 comments)
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/59507/comment/b8710f27_74dc83ca PS7, Line 9: ramstage
Yes I saw an issue with romstage non-serial images but I didn't get a chance to debug yet.
Sure, please raise a bug and link with this CL for visibility
Any reason why we shouldn't call this in ramstage?
Several reasons: 1. Ideally we would like to send and capture the pre-boot data as early as possible. IMO ideally bootblock but due to the fact that we don't want to send HECI command in bootblock hence, my first preference would be romstage early immediately after RO finishes.
2. The more delay you do to send HECI msg, the CSE started doing its own operation like chipset init, fw init, PAVP etc, and ramstage has ample HECI command to send, I just don't want to send one more in ramstage rather than creating a good spread where things would have done earlier is preferred than being late.
3. We might wish to debug CSE boot time regression issue and want to know the CSE boot time early, why to wait for system to boot all the way in ramstage after MRC init rather when you can get those debug timestamp in early romstage.
4. Creating a placeholder where in future we could move pre-reset timestamp retrieving operation in bootblock *without* performing those injection mechanism.
File src/soc/intel/common/block/cse/telemetry.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/46a42059_c7edeb87 PS7, Line 72: BS_PRE_DEVICE
is there a reason why it needs to be in romstage?
added few thoughts in other file.