V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47431 )
Change subject: soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B ......................................................................
Patch Set 8:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... PS7, Line 16: CONFIG_SOC_INTEL_CSE_RW_VERSION
If CONFIG_SOC_INTEL_CSE_RW_VERSION is "" and CONFIG_SOC_INTEL_CSE_RW_FILE is not, then we need to th […]
Done
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... PS7, Line 18: =
:= here and for rest of the version variables.
Done
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... PS7, Line 26: openssl dgst -sha256 -hex $(CSE_RW_PATH) | cut -d " " -f2 | fold -w2 | paste -sd',' -)
May I suggest the following? […]
I tried this out but somehow but i was facing some issue while trying to pass this compile time flag to update .sha256 = {CSE_RW_SHA256}, and will check this again.
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... PS7, Line 27: $(HASH)
"${HASH}"
Done
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/47431/7/src/soc/intel/common/block/... PS7, Line 81: SHA256_DIGEST_SIZE
nit: I think you can use `VB2_SHA256_DIGEST_SIZE` and include vb2_api. […]
Done