[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai.
Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61458

to look at the new patch set (#5).

Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1
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soc/intel/alderlake: Use PMC IPC to disable HECI1

This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.

Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.

Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.

Signed-off-by: Subrata Banik 
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/alderlake/smihandler.c
3 files changed, 3 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61458/5