Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45588 )
Change subject: spd: move mainboard_get_dram_part_num to src/vendor/google/chromeos ......................................................................
spd: move mainboard_get_dram_part_num to src/vendor/google/chromeos
Move mainboard_get_dram_part_num() into src/vendor/google/chromeos to allow mainboards to use it without having to duplicate that code.
Add SPD_PART_NUMBER_IN_CBI Kconfig option to declare whether the SPD Module Part Number (memory part name) is stored in the CBI.
Remove existing mainboard_get_dram_part_num() definitions from individual mainboards and replaced with appropriate SPD_PART_NUMBER_IN_CBI setting.
BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information:
SPD: module part number is K4U6E3S4AA-MGCL
I also built coreboot for hatch and dedede and verified that the build succeeds without error.
Change-Id: Ie173b81b9c9a98f3744cc9da4b034d2251f5589b Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/romstage.c M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/romstage_spd_cbfs.c M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/romstage.c M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/mainboard.c 8 files changed, 34 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/45588/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 79c2995..137247b 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -100,6 +100,9 @@ string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE
+config SPD_PART_NUMBER_IN_CBI + def_bool y + config TPM_TIS_ACPI_INTERRUPT int default 4 # GPE0_DW0_4 (GPP_B4) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index db6f7db..02ebfac 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -21,19 +21,3 @@
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return false; - } - - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store); - return true; -} diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e4e343b..0b456b8 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -148,6 +148,10 @@ default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+config SPD_PART_NUMBER_IN_CBI + def_bool y + default n if ROMSTAGE_SPD_SMBUS + config TPM_TIS_ACPI_INTERRUPT int default 53 # GPE0_DW1_21 (GPP_C21) diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a9a65e9..0dae6cd 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -7,6 +7,7 @@ #include <memory_info.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <spd_bin.h> #include <string.h> #include <variant/gpio.h>
@@ -56,29 +57,3 @@
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } - -void mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - static enum { - PART_NUM_NOT_READ, - PART_NUM_AVAILABLE, - PART_NUM_NOT_IN_CBI, - } part_num_state = PART_NUM_NOT_READ; - - if (part_num_state == PART_NUM_NOT_READ) { - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - part_num_state = PART_NUM_NOT_IN_CBI; - } else { - part_num_state = PART_NUM_AVAILABLE; - } - } - - if (part_num_state == PART_NUM_NOT_IN_CBI) - return; - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store) + 1; -} diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index dda2f4e..040a171 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI @@ -100,6 +101,9 @@ hex default 0x1c000000 # 448 MiB
+config SPD_PART_NUMBER_IN_CBI + def_bool y + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8893785..bec8f47 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -29,17 +29,3 @@
meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; - } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; -} diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17236d..04f68c4 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -16,3 +16,5 @@ verstage-y += watchdog.c romstage-y += watchdog.c ramstage-y += watchdog.c + +romstage-y += mainboard.c diff --git a/src/vendorcode/google/chromeos/mainboard.c b/src/vendorcode/google/chromeos/mainboard.c new file mode 100644 index 0000000..6cc6901 --- /dev/null +++ b/src/vendorcode/google/chromeos/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <spd_bin.h> +#include <string.h> + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + if (google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); + return false; + } + *part_num = part_num_store; + *len = strlen(part_num_store); + return true; +}