Hello Hung-Te Lin, build bot (Jenkins), Paul Menzel, Julius Werner, Derek Waldner, Yu-Ping Wu, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39034
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch ......................................................................
soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch
Because eMCP and discrete DDR devices have different DVFS tables, their EMI bandwidth thresholds should also be different. When the EMI total bandwidth reaches the threshold, the system will notify DVFS module to perform DVFS switch for system performance in low power states.
This patch increases the threshold from 0xa to 0xd for eMCP DDR devices so that DVFS switch will be less likely to happen.
The datasheet of register bwct0 have mistake here, from the hardware design, BW_2ND_INT_BW_THR should be [30:24], not [22:16]. However, the logic of DRAM driver is correct, same as the hardware design, so only the datasheet of reg bwct0's offset is wrong.
BRANCH=kukui BUG=b:142358843 TEST=bootup pass
Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/39034/6