[coreboot-gerrit] Change in coreboot[master]: soc/intel/{adl,apl,cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset...

[Mario Scheithauer (Code Review)]

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45337 )

Change subject: soc/intel/{adl,apl,cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block
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Patch Set 5:
> Patch Set 5:
> > Patch Set 5:
> >
> > @Matt: If you could help me to get this validated quickly on SKL platform
> > @Werner: Possible to check on APL platform
> >
> > I don't have SKL and APL connected remotely in current situation hence i'm working to enable those board for remote test setup. Your help might unblock this.
>
> Hey Subrata.
> We will have a look at this patch and give it a try on one of our APL-mainboard. I will provide feedback in a few hours. Is a successful boot enough or should I take a closer look to something special?

Hi Subrata,
I have tested your patches on mc_apl5.
do_global_reset() does not work at all times.
During mainboard_init() the HECI device is not available.

Log output:
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

In romstage and in mainboard_final (ramstage) the global reset works well.