[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x/raminit: Make programming launch ddr3 specific

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19872 )

Change subject: nb/intel/x4x/raminit: Make programming launch ddr3 specific
......................................................................

nb/intel/x4x/raminit: Make programming launch ddr3 specific

Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/x4x.h
2 files changed, 76 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/19872/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 253b5ee..fc8e5a0 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -194,12 +194,79 @@
    u32 launch2 = 0;
    u32 launch3 = 0;

-	if (s->selected_timings.CAS == 5)
-		launch2 = 0x00220201;
-	else if (s->selected_timings.CAS == 6)
-		launch2 = 0x00230302;
-	else
-		die("Unsupported CAS\n");
+	static const u32 ddr3_launch1_tab[2][3] = {
+		/* 1N */
+		{0x58000007, /* DDR3 800 */
+		 0x58000007, /* DDR3 1067 */
+		 0x58100107}, /* DDR3 1333 */
+		/* 2N */
+		{0x58001117, /* DDR3 800 */
+		 0x58001117, /* DDR3 1067 */
+		 0x58001117} /* DDR3 1333 */
+	};
+
+	static const u32 ddr3_launch2_tab[2][3][6] = {
+		{ /* 1N */
+			/* DDR3 800 */
+			{0x08030000,	/* CL = 5 */
+			 0x0C040100},	/* CL = 6 */
+			/* DDR3 1066 */
+			{0x00000000,	/* CL = 5 */
+			 0x00000000,	/* CL = 6 */
+			 0x10050100,	/* CL = 7 */
+			 0x14260200},	/* CL = 8 */
+			/* DDR3 1333 */
+			{0x00000000,	/* CL = 5 */
+			 0x00000000,	/* CL = 6 */
+			 0x00000000,	/* CL = 7 */
+			 0x14060000,	/* CL = 8 */
+			 0x18070100,	/* CL = 9 */
+			 0x1C280200},	/* CL = 10 */
+
+		},
+		{ /* 2N */
+			/* DDR3 800 */
+			{0x00040101,	/* CL = 5 */
+			 0x00250201},	/* CL = 6 */
+			/* DDR3 1066 */
+			{0x00000000,	/* CL = 5 */
+			 0x00050101,	/* CL = 6 */
+			 0x04260201,	/* CL = 7 */
+			 0x08470301},	/* CL = 8 */
+			/* DDR3 1333 */
+			{0x00000000,	/* CL = 5 */
+			 0x00000000,	/* CL = 6 */
+			 0x00000000,	/* CL = 7 */
+			 0x08070100,	/* CL = 8 */
+			 0x0C280200,	/* CL = 9 */
+			 0x10490300}	/* CL = 10 */
+		}
+	};
+
+	if (s->spd_type == DDR2) {
+		if (s->selected_timings.CAS == 5)
+			launch2 = 0x00220201;
+		else if (s->selected_timings.CAS == 6)
+			launch2 = 0x00230302;
+		else
+			die("Unsupported CAS\n");
+	} else { /* DDR3 */
+		/* Default 2N mode */
+		s->nmode = 2;
+
+		if (s->max_fsb <= FSB_CLOCK_1066MHz)
+			s->nmode = 1;
+		/* 2N on DDR3 1066 with with 2 dimms per channel */
+		if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) &&
+			(BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) ||
+				BOTH_DIMMS_ARE_POPULATED(s->dimms, 1)))
+			s->nmode = 2;
+		launch1 = ddr3_launch1_tab[s->nmode - 1]
+			[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
+		launch2 = ddr3_launch2_tab[s->nmode - 1]
+			[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+			[s->selected_timings.CAS - 5];
+	}

FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
    	MCHBAR32(0x400*i + 0x220) = launch1;
@@ -211,6 +278,8 @@
    MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000;
    MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0;
    MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc;
+	if (s->spd_type == DDR3)
+		MCHBAR32(0x2c4) = MCHBAR32(0x2c4) | 0x100;
 }

static void clkset0(u8 ch, const struct dll_setting *setting)
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 621a685..34fef93 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -290,6 +290,7 @@
    struct timings	selected_timings;
    struct dimminfo	dimms[4];
    u8		spd_map[4];
+	u8		nmode;
 };
 #define BOOT_PATH_NORMAL	0
 #define BOOT_PATH_WARM_RESET	1