[coreboot-gerrit] [S] Change in coreboot[main]: WIP: arch/riscv: add test to set variable for menvcfg

[ron minnich (Code Review)]

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81293?usp=email )

Change subject: WIP: arch/riscv: add test to set variable for menvcfg
......................................................................

WIP: arch/riscv: add test to set variable for menvcfg

there are many variant features on SoCs.

This CL demonstrates a simple way to test feature existence
with low effort.

It correctly detects the menvcfg register.

Signed-off-by: Ronald G Minnich

Change-Id: If9f5db74d7467ab00044d20050531bcb511cce39
clang-formatted-by: Ronald G Minnich
---
M src/arch/riscv/include/arch/encoding.h
M src/arch/riscv/payload.c
M src/arch/riscv/ramstage.S
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/81293/1

diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 4f01e5c..6ab38bb 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -800,6 +800,8 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MENVCFG 0x30a
+#define CSR_MENVCFGH 0x31a
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
@@ -1292,6 +1294,8 @@
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(menvcfg, CSR_MENVCFG)
+DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 7c6e0f4..636462f 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -11,6 +11,8 @@
 #include <mcall.h>
 #include <vm.h>

+uintptr_t has_menvcfg;
+
 /* Run OpenSBI and let OpenSBI hand over control to the payload */
 void run_payload_opensbi(struct prog *prog, void *fdt, struct prog *opensbi, int payload_mode)
 {
@@ -68,6 +70,9 @@
    	 */
    	close_pmp();

+		printk(BIOS_EMERG, "has_menvcfg %ld\n", has_menvcfg);
+		if (has_menvcfg) {
+		}
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
    	/* Trap vector base address point to the payload */
    	write_csr(stvec, doit);
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
index 954b155..0557d8c 100644
--- a/src/arch/riscv/ramstage.S
+++ b/src/arch/riscv/ramstage.S
@@ -35,6 +35,16 @@
    #NOTE a1 contains FDT and should not be cluttered above
    call hls_init

+	# determine HART properties. It is easiest done here.
+	la t1, has_menvcfg
+	li t3, 1
+	STORE x0, 0(t1)
+	la t0, 1f
+	csrw mtvec, t0
+	csrs menvcfg, t0
+	STORE t3, 0(t1)
+1:
+
    li   a0, CONFIG_RISCV_WORKING_HARTID
    call smp_pause

@@ -54,3 +64,5 @@
    .weak exit_car
 exit_car:
    ret
+
+.globl has_menvcfg