HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5881
-gerrit
commit ee8b2494c78b55c021c951bbfbcb8094b00ddb9e Author: Elyes HAOUAS ehaouas@noos.fr Date: Mon Jun 16 20:39:14 2014 +0200
New Board based NEC ECS 945G M4 (LGA775 i945GC i82801gx w83627ehg)
Switch to DYNAMIC_CBMEM. (board not supported yet)
Change-Id: I7b00251e332ac005918cf7c3ed4bef8878bd145b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/nec/945g-m4/Kconfig | 42 +++++++ src/mainboard/nec/945g-m4/romstage.c | 227 +++++++++++++++++++++++++++++++++++ 2 files changed, 269 insertions(+)
diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..2d74440 --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ +/* values found unsing ./inteltool -g on nec bios */ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0xebffffbf, DEFAULT_GPIOBASE + GP_LVL); + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + GPI_INV); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x000000f0, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0x000000f7, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, LPC_EN, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); +} + +static void rcba_config(void) +{ + /* ./inteltool -r */ + + /* Set up virtual channel 0 */ + RCBA32(V0CTL) = 0x80000001; + RCBA32(V1CAP) = 0x03128010; + +/* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(D28IP) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000001; + /* dev irq route register */ + RCBA16(D31IR) = 0x3241; + RCBA16(D30IR) = 0x0132; + RCBA16(D29IR) = 0x3210; + RCBA16(D28IR) = 0x0237; + RCBA16(D27IR) = 0x0000; + /* Enable IOAPIC */ + RCBA32(0x31fc) |= 3 << 24; + /* Enable upper 128bytes of CMOS */ + RCBA32(RC) = (1 << 2); + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; +} +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /*./inteltool -r on vendor bios*/ + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(FD) |= (1 << 0); +// RCBA16(0x0200) = 0x0110; + RCBA32(0x0200) = 0x01102008; + RCBA8(0x2027) = 0x00; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +void main(unsigned long bist) +{ + + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + if (bist == 0) + enable_lapic(); + ich7_enable_lpc(); + /* Set up the console */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif /* CONFIG_HAVE_ACPI_RESUME */ + } + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(boot_mode, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + /* Chipset Errata! */ + fixup_i945_errata(); + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + + sdram_dump_mchbar_registers(); + dump_pci_device(PCI_DEV(0,0,0)); + //dump_pci_device(PCI_DEV(0,0x1f, 0)); + ram_check_nodie(0<<20,0); + ram_check_nodie(2<<20,0); + ram_check_nodie(1<<20,0); + +// quick_ram_check(); + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); +#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */ + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + } +#endif /* CONFIG_HAVE_ACPI_RESUME */ +}