Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21764
Change subject: arch/riscv: Return from trap_handler instead of jumping out ......................................................................
arch/riscv: Return from trap_handler instead of jumping out
Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer j.neuschaefer@gmx.net --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 3 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21764/1
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 78b98e4..1f13bed 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,6 @@ } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); }
static const char *const exception_names[] = { @@ -210,16 +209,16 @@ case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); handle_misaligned_load(tf); - break; + return; case CAUSE_MISALIGNED_STORE: print_trap_information(tf); handle_misaligned_store(tf); - break; + return; case CAUSE_SUPERVISOR_ECALL: /* Don't print so we make console putchar calls look the way they should */ handle_supervisor_call(tf); - break; + return; default: printk(BIOS_EMERG, "================================\n"); printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); @@ -262,7 +261,6 @@
// return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); }
void handle_misaligned_store(trapframe *tf) { @@ -290,5 +288,4 @@
// return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5add7ba..601862d 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -137,7 +137,6 @@ move a0,sp jal trap_handler
- .global trap_return trap_return: csrr a0, mscratch restore_regs