Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49821 )
Change subject: intel/baytrail,braswell,broadwell: Add const qualifier for power_state ......................................................................
intel/baytrail,braswell,broadwell: Add const qualifier for power_state
Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/pch/power_state.c 4 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49821/1
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index b0d380c..e9513cd 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -59,7 +59,7 @@ }
/* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(struct chipset_power_state *ps) +static int chipset_prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 2cf9afa..3f38de8 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -11,7 +11,7 @@ void punit_init(void);
/* romstage.c functions */ -int chipset_prev_sleep_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(const struct chipset_power_state *ps);
/* Values for FSP's PcdMemoryTypeEnable */ #define MEM_DDR3 0 diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 1738679..5a1aa0a 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -57,7 +57,7 @@ }
/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int chipset_prev_sleep_state(struct chipset_power_state *ps) +int chipset_prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index cb1d3e5..12bee7d 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -33,7 +33,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
/* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int prev_sleep_state(struct chipset_power_state *ps) +static int prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0;