[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use ACPI timer config from soc common code

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36064 )

Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code
......................................................................

soc/intel/cannonlake: Use ACPI timer config from soc common code

Replace the usage of structure member "PMTimerDisabled" of struct
"soc_intel_cannonlake_config" in soc code with ACPI timer config
defined under soc/intel/common/block/timer/Kconfig.

BUG=none
TEST=none

Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/fsp_params.c
6 files changed, 4 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 7382209..d7c975f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -56,8 +56,6 @@
    # putting it under register "common_soc_config" in overridetree.cb file.
    register "common_soc_config.pch_thermal_trip" = "77"

-	register "PmTimerDisabled" = "1"
-
    # VR Settings Configuration for 4 Domains
    #+----------------+-------+-------+-------+-------+
    #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 6846594..22a8a40 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -179,7 +179,7 @@
    const struct soc_intel_cannonlake_config *config;
    config = config_of_soc();

-	if (!config->PmTimerDisabled) {
+	if (CONFIG_USE_ACPI_PM_TIMER) {
    	fadt->pm_tmr_blk = pmbase + PM1_TMR;
    	fadt->pm_tmr_len = 4;
    	fadt->x_pm_tmr_blk.space_id = 1;
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b937699..29ce25a 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -267,7 +267,6 @@
     * 0x02000000 - 32MiB and beyond
     */
    uint32_t PrmrrSize;
-	uint8_t PmTimerDisabled;

/*
     * SLP_S3 Minimum Assertion Width Policy
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index c58b9ad..bfb6bd1 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -390,7 +390,7 @@
    config = config_of_soc();

/* Enable PM timer emulation only if ACPI PM timer is disabled */
-	if (!config->PmTimerDisabled)
+	if (CONFIG_USE_ACPI_PM_TIMER)
    	return;
    /*
     * The derived frequency is calculated as follows:
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 115b732..3ffc942 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -86,7 +86,7 @@
     */
    config = config_of_soc();
    pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
+	if (!CONFIG_USE_ACPI_PM_TIMER) {
    	reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
    	reg8 |= (1 << 1);
    	write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index b580620..2dd85ed 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -380,7 +380,7 @@
    params->SataPwrOptEnable = config->satapwroptimize;

/* Disable PCH ACPI timer */
-	params->EnableTcoTimer = !config->PmTimerDisabled;
+	params->EnableTcoTimer = CONFIG_USE_ACPI_PM_TIMER;

/* Apply minimum assertion width settings if non-zero */
    if (config->PchPmSlpS3MinAssert)