build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62092 )
Change subject: nb/amd/amdfam10/bootblock.c: Change to standard PCI access functions ......................................................................
Patch Set 1:
(21 comments)
File src/northbridge/amd/amdfam10/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/11779f69_916e2964 PS1, Line 72: id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/d3d360de_71d2f4d9 PS1, Line 72: id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/e30a00f6_558990cf PS1, Line 81: hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/77830f16_bfe327c0 PS1, Line 81: hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/d6d800b6_87997724 PS1, Line 88: pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/e756b03a_7b6bedf5 PS1, Line 88: pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/07a33cf5_7faedf56 PS1, Line 92: cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/cd024d14_9d463968 PS1, Line 92: cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/39038ba9_9dd85218 PS1, Line 98: flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/be212ae6_e0009bc6 PS1, Line 98: flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/a2612eea_b947789a PS1, Line 99: pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/b768b4e7_53061d68 PS1, Line 99: pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/7a43cd3b_e6ee2713 PS1, Line 100: flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/7dee3625_aa9ee825 PS1, Line 100: flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/7f7130ff_cb5f8769 PS1, Line 131: pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/7c0a67c9_6ffeeb92 PS1, Line 153: pci_write_config16(devx, pos + ctrl_off, ctrl); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/60ee39e5_d62dd4fa PS1, Line 154: ctrl = pci_read_config16(devx, pos + ctrl_off); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/349873b1_ab413b9b PS1, Line 174: flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/410a7f41_db834997 PS1, Line 174: flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/0ddce279_a0871990 PS1, Line 174: flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-141269): https://review.coreboot.org/c/coreboot/+/62092/comment/416ca221_840701e2 PS1, Line 177: pci_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); line over 96 characters