Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48286 )
Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... PS17, Line 101: CONFIG_IA32_L3_MASK_1_DEFAULT
If we don't have the values for other platforms yet, then this needs to be guarded by CONFIG_SOC_INT […]
I think it is generally wrong to include SoC specific config checks in common code. Since this is equally applicable to all SoCs using this CAR setup, it would be good to update all the impacted SoCs to provide the right configuration.
BTW, same comment as SF_MASK, why are we not using way # to calculate this mask at runtime?
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... PS17, Line 255: 0xffff
The eNEM programming instructions said to set these MSRs back to their reset default values, which c […]
Have we confirmed that? Both L3_MASK and SF_QOS_MASK are related to capacity bit masks which are different dependent on number of ways.
BTW, EDS Vol2 says that the default value for SF_QOS_MASK is 0FFFFFFFh which is different than what is being programmed here.