[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/acpi: Add provision for multiple PCI segments

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40335 )

Change subject: soc/intel/common/block/acpi: Add provision for multiple PCI segments
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Patch Set 5:
> > Does ICL really have multiple PCI segments?
>
> If a platform supports more than 256 buses, then it should support multi-segment.
> It aligns with the below description in the EDS.

I guess that's a no (for ICL).
> TGL as you know supports 2 segments,

Nope, I didn't know that.
> 1 for TBT and 1 for the rest of the devices which adds up to a total of 512 buses.

Thanks for mentioning this. Even if it is not your reason
for this change, please put this information into the commit
message. It makes a huge difference: without it, your changes
look like added complexity for naught; with it, there is a
reason and reviewers can do their job.