Attention is currently required from: Jason Nien, Martin Roth.
Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73295 )
Change subject: mb/google/skyrim: Whiterun/Winterhold PCIe lanes 2-3 are unused ......................................................................
mb/google/skyrim: Whiterun/Winterhold PCIe lanes 2-3 are unused
Mark PCIe lanes 2 & 3 as unused.
BUG=None TEST=Boot Whiterun
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I95e80ad0335d09b0dbfc678d0c710d2fbd10bf95 --- M src/mainboard/google/skyrim/variants/whiterun/Makefile.inc A src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.inc A src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 4 files changed, 187 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/73295/1
diff --git a/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc index db72b15..26b1ce2 100644 --- a/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc @@ -2,4 +2,7 @@
subdirs-y += ./memory
+romstage-y += port_descriptors.c + ramstage-y += gpio.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c b/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c new file mode 100644 index 0000000..5920fe6 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 3, + .clk_req = CLK_REQ2, + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 3, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { /* Unused */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 2, + .end_logical_lane = 3, + .turn_off_unused_lanes = true, + }, +}; + +static const fsp_ddi_descriptor ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI/DP */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - Unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + }, +}; + +void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) +{ + *dxio_num = ARRAY_SIZE(dxio_descriptors); + *dxio_descs = dxio_descriptors; +} + +void variant_get_ddi_descriptor(const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *ddi_num = ARRAY_SIZE(ddi_descriptors); + *ddi_descs = ddi_descriptors; +} diff --git a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc index db72b15..26b1ce2 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc @@ -2,4 +2,7 @@
subdirs-y += ./memory
+romstage-y += port_descriptors.c + ramstage-y += gpio.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c new file mode 100644 index 0000000..5920fe6 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 3, + .clk_req = CLK_REQ2, + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 3, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { /* Unused */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 2, + .end_logical_lane = 3, + .turn_off_unused_lanes = true, + }, +}; + +static const fsp_ddi_descriptor ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI/DP */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - Unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + }, +}; + +void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) +{ + *dxio_num = ARRAY_SIZE(dxio_descriptors); + *dxio_descs = dxio_descriptors; +} + +void variant_get_ddi_descriptor(const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *ddi_num = ARRAY_SIZE(ddi_descriptors); + *ddi_descs = ddi_descriptors; +}