[coreboot-gerrit] Change in coreboot[master]: lib/spd_bin: Correct LPDDR3 SPD information

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 15 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/1

diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index a1d75ef..45b1b4c 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -32,7 +32,16 @@

static bool is_memory_type_ddr4(int dram_type)
 {
-	return (dram_type == SPD_DRAM_DDR4);
+	switch (dram_type) {
+	case SPD_DRAM_DDR3:
+	case SPD_DRAM_LPDDR3_INTEL:
+		return false;
+	/* LPDDR3, LPDDR4 and DDR4 are share the same attributes */
+	case SPD_DRAM_LPDDR3_JEDEC:
+	case SPD_DRAM_DDR4:
+	case SPD_DRAM_LPDDR4:
+		return true;
+	}
 }

static const char *spd_get_module_type_string(int dram_type)
@@ -57,14 +66,14 @@
    static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
    int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
    switch (dram_type) {
-	/* DDR3 and LPDDR3 has the same bank definition */
+	/* DDR3 and LPDDR3_Intel have the same bank definition */
    case SPD_DRAM_DDR3:
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	if (index >= ARRAY_SIZE(ddr3_banks))
    		return -1;
    	return ddr3_banks[index];
-	/* DDR4 and LPDDR4 has the same bank definition */
+	/* LPDDR3, LPDDR4 and DDR4 have the same bank definition */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	if (index >= ARRAY_SIZE(ddr4_banks))
@@ -144,11 +153,12 @@
    	spd_name[DDR3_SPD_PART_LEN] = 0;
    	break;
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
    		LPDDR3_SPD_PART_LEN);
    	spd_name[LPDDR3_SPD_PART_LEN] = 0;
    	break;
+	/* LPDDR3, LPDDR4 and DDR4 have the same part number offset */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);