Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Rob Barnes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 )
Change subject: mb/google/guybrush: Add SoC thermal zone ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/54134/comment/d0fb0ae6_d10ec7a1 PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end
Though, I wonder if a `Notify(EC0, 0x80)` would cause the OS to reevaluate the child ThermalZones...
The CrOS EC already has a `notify` handler in the kernel which is currently for MKBP processing, so I'm not sure that would work.
I need to read up on the thermal zones in ACPI... Intel uses DPTF which borrows a lot from it but is still quite different.
acpigen_write_TMP method into `struct device_operations`.
you mean as a new callback, or assigned to which one? the SSDT generation?