Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph, Tim Chu.
Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 )
Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 19:
(3 comments)
File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/52090/comment/52420baa_1a93d891
PS18, Line 27: , 8, // 0x40 - 0x48 Hest log buffer
Where in SMM is this being used? I can't see it.
It's in the SOC portion which I cannot upstream until we get approval from HW vendor.
File src/soc/intel/xeon_sp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/52090/comment/fbbc8b72_325c73dd
PS18, Line 19: ifeq ($(CONFIG_SOC_INTEL_XEON_RAS),y)
: subdirs-y += ras
: endif
Much simpler: […]
Done...
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/18a3b736_edcefba4
PS18, Line 149: * +--------------------------+ cbmem_top
: * | HEST ELOG | (CONFIG_ERROR_LOG_BUFFER_SIZE)
: * +--------------------------+
Here the HEST ELOG is below cbmem_top, but in the code it looks like it is above cbmem_top. […]
1. Done...corrected the map so that HEST ELOG is above cbmem_top.
2. Yes, it cannot be part of CBMEM because in the E820 table, CBMEM is labeled as type16 memory (Unknown to the OS) and therefore ACPI drivers fail to acknowledge this memory and generate ACPI errors, unable to load HEST.
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