Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36058 )
Change subject: soc/skylake/vr_config: fix VR config for KBL-U CPUs ......................................................................
soc/skylake/vr_config: fix VR config for KBL-U CPUs
These changes are in accordance with the documentation: [1] page 106, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006
Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 15 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36058/1
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index b78d336..3cfa70e 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -135,15 +135,17 @@ * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19 * SKL-U (15W) GT2 dual 4.5 29 31 * - * KBL-U/R + OPC (28W) GT3 dual 5.1 32 57/19 - * KBL-U/R + OPC (15W) GT3 dual 5.1 32 57/19 + * KBL-U + OPC (28W) GT3 dual 5.1 32 57/19 + * KBL-U + OPC (15W) GT3 dual 5.1 32 57/19 + * KBL-U (15W) GT1/2 dual 4.5 32 31 + * KBL-U [*] (15W) GT1 quad 4.5 29 31 * * KBL-U/R (15W) GT2 quad 6 64 31 - * KBL-U/R (15W) GT1/2 dual 4.5 32 31 - * KBL-U/R (15W) GT2 quad 4.5 29 31 * * SKL/KBL-Y (6W) 4.1 24 24 * SKL/KBL-Y (4.5W) 4.1 24 24 + * + * [*] Pentium/Celeron CPUs with HD Graphics 610 */
switch (mch_id) { @@ -234,10 +236,17 @@ case PCI_DEVICE_ID_INTEL_KBL_ID_U: { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 0, 31, 31);
- if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || - (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) + if (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM) icc_max[VR_IA_CORE] = VR_CFG_AMP(29);
+ else if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { + const uint16_t icc_max_gt3[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(5.1, 32, 0, 57, 19); + + return icc_max_gt3[domain]; + } + return icc_max[domain]; } default: