Attention is currently required from: Nico Huber, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42434 )
Change subject: [WIP] x86/lapic: Set EXTINT on BSP only ......................................................................
Patch Set 5:
(3 comments)
Patchset:
PS5: Felix, I'd like to reuse Change-Id from this with CB:55701.
File src/cpu/x86/lapic/lapic.c:
https://review.coreboot.org/c/coreboot/+/42434/comment/148dfab5_032bf5e2 PS5, Line 29: | LAPIC_SPIV_ENABLE); Sets spurious interrupt to vector 0? And LVT0 for AP used vector 0 too?
10.9 SPURIOUS INTERRUPT
Do not program an LVT or IOAPIC RTE with a spurious vector even if you set the mask bit. A spurious vector ISR does not do an EOI. If for some reason an interrupt is generated by an LVT or RTE entry, the bit in the in-service register will be left set for the spurious vector. This will mask all interrupts at the same or lower priority
https://review.coreboot.org/c/coreboot/+/42434/comment/7537f320_ec347774 PS5, Line 34: lvt0_val |= LAPIC_DELIVERY_MODE_FIXED | LAPIC_LVT_MASKED;
I was much surprised when I learned what EXTINT means. It's about the […]
10.5.2 Valid Interrupt Vectors
When an interrupt vector in the range of 0 to 15 is sent or received through the local APIC, the APIC indicates an illegal vector in its Error Status Register (see Section 10.5.3, “Error Handling”)
When an illegal vector value (0 to 15) is written to an LVT entry and the delivery mode is Fixed (bits 8-11 equal 0), the APIC may signal an illegal vector error, without regard to whether the mask bit is set or whether an interrupt is actually seen on the input.
Figure 10-8. Local Vector Table (LVT) Value After Reset: 0001 0000H