Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47056 )
Change subject: Support for Zotac AD04 added (initial commit) ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Bi... File src/mainboard/zotac/ad04/BiosCallOuts.c:
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Bi... PS1, Line 37: static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) : { : AGESA_READ_SPD_PARAMS *info = ConfigPtr; : : if (!ENV_ROMSTAGE) : return AGESA_UNSUPPORTED; : : u8 index = get_spd_offset(); : : if (info->MemChannelId > 0) : return AGESA_UNSUPPORTED; : if (info->SocketId != 0) : return AGESA_UNSUPPORTED; : if (info->DimmId != 0) : return AGESA_UNSUPPORTED; : : /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ : if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) : die("No SPD data\n"); : : return AGESA_SUCCESS; : } You probably want to do what e350m1 does here instead
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Kc... File src/mainboard/zotac/ad04/Kconfig:
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Kc... PS1, Line 20: select MAINBOARD_HAS_LPC_TPM I don't think this board has a TPM?
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Kc... PS1, Line 28: apu1 nope
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/Kc... PS1, Line 63: choice : prompt "J19 pins 1-10" : default APU1_PINMUX_OFF_C : : config APU1_PINMUX_OFF_C : bool "disable" : : config APU1_PINMUX_GPIO0 : bool "GPIO" : : config APU1_PINMUX_UART_C : bool "UART 0x3e8" : : endchoice : : config UART_C_RS485 : bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C : : choice : prompt "J19 pins 11-20" : default APU1_PINMUX_OFF_D : : config APU1_PINMUX_OFF_D : bool "disable" : : config APU1_PINMUX_GPIO1 : bool "GPIO" : : config APU1_PINMUX_UART_D : bool "UART 0x2e8" : : endchoice : : config UART_D_RS485 : bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D Remove these and any board code using these options
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/gp... File src/mainboard/zotac/ad04/gpio_ftns.c:
PS1: This shouldn't be needed.
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/ro... File src/mainboard/zotac/ad04/romstage.c:
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/ro... PS1, Line 20: /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ : bdata = pm_read8(SB_PMIOA_REGEA); : bdata &= 0xfe; //clear bit 0 : bdata |= 0x01; //set bit 0 : pm_write8(SB_PMIOA_REGEA, bdata); : : //configure required GPIOs : configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); : configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); : configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT); : configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT); : configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT); : configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT); : configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT); : configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); : configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); : configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); This can be skipped for now
https://review.coreboot.org/c/coreboot/+/47056/1/src/mainboard/zotac/ad04/sp... File src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex:
PS1: No onboard memory, this can be removed