Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46115 )
Change subject: soc/intel/jasperlake: Remove GPIO community 2 from DSDT ......................................................................
soc/intel/jasperlake: Remove GPIO community 2 from DSDT
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns these addresses based on the BARs enumerated by coreboot. Coreboot was defining communities 0, 1, 2, 4, and 5. This meant the kernel was not controlling GPIOs in communities 4 and 5, since the resources were wrong.
Remove community 2 for now. We can add it back if the kernel ends up needing it.
BUG=b:169444894 TEST=Test controlling GPP_E5, verify actually toggles register.
Signed-off-by: Evan Green evgreen@chromium.org Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 --- M src/soc/intel/jasperlake/acpi/gpio.asl 1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46115/1
diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index e39ac8a..421abc3 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -18,7 +18,6 @@ { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM2) Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -39,12 +38,6 @@ BAS1 = ^^PCRB (PID_GPIOCOM1) LEN1 = GPIO_BASE_SIZE
- /* GPIO Community 2 */ - CreateDWordField (^RBUF, ^COM2._BAS, BAS2) - CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - BAS2 = ^^PCRB (PID_GPIOCOM2) - LEN2 = GPIO_BASE_SIZE - /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4)