build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 17:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 55: PCH_PCIE_RP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 56: CPU_PCIE_RP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 27: die ("Unsupported type!"); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 62: m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; trailing whitespace