Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/e63a91a5_6a351ef5
PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
As CLKREQ 6 is used for both PCH LAN and RP8 hence we need to make it as free running clock rather assign to particular RP as other PCIe CLK does
Wait.. did you mean CLKSRC7 is used for both PCH LAN and RP8? I don't understand the intent behind sharing of CLKREQ for PCH LAN and RP8.
For RP8 CLKSRC is 7 and CLKREQ is 6 which is muxed between LAN and RP8
Also, what is the advantage of setting CLKREQ for the free running clock source?
Device on PCH DT slot won't work if we don't configure the CLKREQ accordingly
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