Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40584 )
Change subject: mb/google/voteer: Enable DevSlp for SATA port1 ......................................................................
mb/google/voteer: Enable DevSlp for SATA port1
BUG=b:152893285 BRANCH=none TEST=Build and boot to OS volteer with Intel SATA and reboot from OS console
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 12ae87a..b689663 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -77,6 +77,7 @@ register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1"
register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci,