Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30863
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPU's support a non-eviction mode that ought to be used during cache as ram setup.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/1
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d1cc80f..1ea5a34 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,5 +1,7 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + help + Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7993294..868f6e5 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -postcar-y += ../car/p4-netburst/exit_car.S +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c