[coreboot-gerrit] Change in coreboot[master]: ec/google/chromeec : Enable TCSS port set flag

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38726 )

Change subject: ec/google/chromeec : Enable TCSS port set flag
......................................................................

ec/google/chromeec : Enable TCSS port set flag

Kernel needs a way to know if coreboot initialized any Type-C SubSytem
ports during boot. This API allows EC to store this information and
pass it on to the Kernel when it checks for port status.

BUG = NONE
BRANCH = NONE
TEST = Built coreboot image and tested that the flag was being set

Change-Id: Idfc1e6515411fab75b7da1b60775c26d17089c1c
Signed-off-by: Brandon Breitenstein 
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_commands.h
M src/soc/intel/tigerlake/early_tcss.c
4 files changed, 52 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38726/1

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 9bcb4a3..4dd5aaf 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1472,6 +1472,31 @@
    return 0;
 }

+int google_chromeec_set_early_tcss_state(int port, int state)
+{
+	struct ec_params_usb_pd_set_tcss_state params = {
+		.port = port,
+		.tcss_state = state,
+	};
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_USB_PD_SET_TCSS_STATE,
+		.cmd_version = 0,
+		.cmd_data_in = &params,
+		.cmd_size_in = sizeof(params),
+		.cmd_data_out = NULL,
+		.cmd_dev_index = 0,
+	};
+
+	int rv;
+
+	rv = google_chromeec_command(&cmd);
+	if (rv)
+		return rv;
+
+	return 0;
+}
+
+
 void google_chromeec_init(void)
 {
    google_chromeec_log_uptimeinfo();
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index f25c0b3..9c66037 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -49,6 +49,9 @@
 uint8_t google_chromeec_pd_get_port_info(int port);
 /* Returns data role and type of device connected */
 int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, int *dp_mode);
+/* Set the TCSS early init state */
+int google_chromeec_set_early_tcss_state(int port, int state);
+
 int google_chromeec_wait_for_displayport(long timeout);

/* Device events */
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index ace8e05..f84eb99 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -5249,7 +5249,7 @@
    char state[32];
    uint8_t cc_state;       /* enum pd_cc_states representing cc state */
    uint8_t dp_mode;        /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
-	uint8_t reserved;       /* Reserved for future use */
+	uint8_t tcss_state;     /* Early boot state of Type-C Sub Systems */
    uint8_t control_flags;  /* USB_PD_CTRL_*flags */
    uint8_t cable_speed;    /* TBT_SS_* cable speed */
    uint8_t cable_gen;      /* TBT_GEN3_* cable rounded support */
@@ -5318,6 +5318,18 @@
    uint8_t port_count;
 } __ec_align1;

+/*
+ * This command synchronizes the coreboot and Kernel TCSS (Type-C Sub Systems)
+ * states by saving the coreboot's early boot TCSS state of USB-C ports. When
+ * the Kernel boots, it determines the next TCSS state based on the coreboot's
+ * early boot state available in EC.
+ */
+#define EC_CMD_USB_PD_SET_TCSS_STATE 0x0106
+struct ec_params_usb_pd_set_tcss_state {
+	uint8_t port;
+	uint8_t tcss_state;
+} __ec_align1;
+
 /* Write USB-PD device FW */
 #define EC_CMD_USB_PD_FW_UPDATE 0x0110

diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c
index 8965f0b..4dbb2a1 100644
--- a/src/soc/intel/tigerlake/early_tcss.c
+++ b/src/soc/intel/tigerlake/early_tcss.c
@@ -28,6 +28,8 @@

#define USB_PD_MUX_TBT_ACTIVE_CABLE   BIT(0) /* Active/Passive Cable */

+#define TCSS_PORT_SET 0x1
+
 /* DP Mode pin definitions */
 #define MODE_DP_PIN_A BIT(0)
 #define MODE_DP_PIN_B BIT(1)
@@ -64,6 +66,7 @@
    uint32_t tcss_res = 0;
    int req_size;
    int ret = 0;
+	int port_state = 0;

/* Set the PMC IPC command to USB and Sub Command to 0 */
    cmd.ipc_cmd.cmd = PMC_IPC_USBC_CMD_ID;
@@ -86,6 +89,7 @@
    	memcpy(wbuf, tcss_req, req_size);

cmd.ipc_cmd.len = req_size;
+		port_state = TCSS_PORT_SET;

ret = pmc_send_ipc_cmd(&cmd.cmd, req_size, wbuf, rbuf);
    }
@@ -115,6 +119,7 @@
    	memcpy(wbuf, tcss_req, req_size);

cmd.ipc_cmd.len = req_size;
+		port_state = TCSS_PORT_SET;

ret = pmc_send_ipc_cmd(&cmd.cmd, req_size, wbuf, rbuf);
    }
@@ -122,6 +127,12 @@
    if (ret)
    	printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret);

+	if (port_state)
+		ret = google_chromeec_set_early_tcss_state(port, port_state);
+
+	if (ret)
+		printk(BIOS_ERR, "Port %d flag was not correctly set by ec\n", port);
+
    printk(BIOS_DEBUG, "Port %d tcss_res=0x%x", port, tcss_res);
 }